Intel asserted its claim over the open and virtual radio access network (RAN) markets at MWC Barcelona 2022 where the chipmaker unpacked a bevy of telco-focused silicon.To get more latest news about intel, you can visit shine news official website.
The updates included a pair of new Xeon D processors, specifically optimized for SDN and edge applications, including RAN, network edge, and artificial intelligence (AI).Intel claims the new chips address growing demand for edge compute, with the chipmaker expecting more than half of all data processing to take place outside of traditional data centers by 2025.
“One of the hottest workloads is inference,” Dan Rodriguez, corporate VP of Intel’s Network Platforms Group, said during his keynote. “Think about all the examples, factories examining products, retail stores that are monitoring inventory and foot traffic, communities creating smart and safe places for residents, networking applications and crypto, and packet processing like SASE and SD-WAN.”
The new Xeon D processors are designed to realize this opportunity, and introduce a number of new features intended to make them attractive to network operators, including specialized AI accelerator blocks with support for 512-bit advanced vector extensions (AVX 512).
AVX 512, which is designed to accelerate large vector calculations common in machine learning workloads, has been Intel’s trump card over rival AMD for some time. However, AMD will launch its first chips with AVX 512 support later this year.
Intel’s Xeon D-1700 and D-2700 processor families bring these AI capabilities to the networking and edge markets.It’s the “first Intel SoC designed from the ground up for software defined network edge,” Rodriguez said.
In addition to AI, the processors also sport an integrated Ethernet controller capable of supporting connections up to 100 Gb/s. This eliminates the need for standalone NICs in space- or power-constrained applications, where high throughput may still be required.
However, for applications that do require external expansion cards, the chips support up to 56 PCIe Gen. 4.0 lanes and SKUs ranging from four to 20 processor cores.These chips are also Intel’s first Xeon D processors to feature the company’s 10-nanometer Sunny Cove core architecture, which offers significant power savings and performance advantages over older 14-nanometer designs.
This is the same core architecture powering Intel’s third-generation Xeon Scalable processors announced last year. Sunny Cove actually made its appearance more than two years ago in Intel’s 10th generation Core-series mobile processors.Intel’s telco-focused Xeons won’t be stuck with a nearly two year old architecture for long. At MWC Barcelona, the chipmaker offered a glimpse into the expanded role its next-generation Xeon Scalable processor family will play in the virtual RAN and open RAN space.
“In the march towards software-defined everything, vRAN is inevitable, but 10 years ago it was unthinkable,” said Nick McKeown, SVP of Intel’s network and edge group.The architecture will be among Intel’s most radical to date and see the chipmaker abandon its long heritage of monolithic dies in favor of an AMD-style chiplet architecture.
The new chips, slated for release early this year, are expected to offer significantly higher core counts, support for on-die high-bandwidth memory (HBM), DDR5 memory, and PCIe Gen. 5.0.And at MWC Barcelona, Intel revealed for the first time plans for telco-specific SKUs with silicon-level optimizations for RAN signal processing and support for large massive MIMO deployments, including 64 transmit, 64 receive antenna arrays.
Intel claims these signal processing optimizations will allow for a twofold improvement in network capacity over previous generation Xeon Scalable processors.
Intel asserted its claim over the open and virtual radio access network (RAN) markets at MWC Barcelona 2022 where the chipmaker unpacked a bevy of telco-focused silicon.To get more latest news about intel, you can visit shine news official website.
The updates included a pair of new Xeon D processors, specifically optimized for SDN and edge applications, including RAN, network edge, and artificial intelligence (AI).Intel claims the new chips address growing demand for edge compute, with the chipmaker expecting more than half of all data processing to take place outside of traditional data centers by 2025.
“One of the hottest workloads is inference,” Dan Rodriguez, corporate VP of Intel’s Network Platforms Group, said during his keynote. “Think about all the examples, factories examining products, retail stores that are monitoring inventory and foot traffic, communities creating smart and safe places for residents, networking applications and crypto, and packet processing like SASE and SD-WAN.”
The new Xeon D processors are designed to realize this opportunity, and introduce a number of new features intended to make them attractive to network operators, including specialized AI accelerator blocks with support for 512-bit advanced vector extensions (AVX 512).
AVX 512, which is designed to accelerate large vector calculations common in machine learning workloads, has been Intel’s trump card over rival AMD for some time. However, AMD will launch its first chips with AVX 512 support later this year.
Intel’s Xeon D-1700 and D-2700 processor families bring these AI capabilities to the networking and edge markets.It’s the “first Intel SoC designed from the ground up for software defined network edge,” Rodriguez said.
In addition to AI, the processors also sport an integrated Ethernet controller capable of supporting connections up to 100 Gb/s. This eliminates the need for standalone NICs in space- or power-constrained applications, where high throughput may still be required.
However, for applications that do require external expansion cards, the chips support up to 56 PCIe Gen. 4.0 lanes and SKUs ranging from four to 20 processor cores.These chips are also Intel’s first Xeon D processors to feature the company’s 10-nanometer Sunny Cove core architecture, which offers significant power savings and performance advantages over older 14-nanometer designs.
This is the same core architecture powering Intel’s third-generation Xeon Scalable processors announced last year. Sunny Cove actually made its appearance more than two years ago in Intel’s 10th generation Core-series mobile processors.Intel’s telco-focused Xeons won’t be stuck with a nearly two year old architecture for long. At MWC Barcelona, the chipmaker offered a glimpse into the expanded role its next-generation Xeon Scalable processor family will play in the virtual RAN and open RAN space.
“In the march towards software-defined everything, vRAN is inevitable, but 10 years ago it was unthinkable,” said Nick McKeown, SVP of Intel’s network and edge group.The architecture will be among Intel’s most radical to date and see the chipmaker abandon its long heritage of monolithic dies in favor of an AMD-style chiplet architecture.
The new chips, slated for release early this year, are expected to offer significantly higher core counts, support for on-die high-bandwidth memory (HBM), DDR5 memory, and PCIe Gen. 5.0.And at MWC Barcelona, Intel revealed for the first time plans for telco-specific SKUs with silicon-level optimizations for RAN signal processing and support for large massive MIMO deployments, including 64 transmit, 64 receive antenna arrays.
Intel claims these signal processing optimizations will allow for a twofold improvement in network capacity over previous generation Xeon Scalable processors.